Key Management Engine With an SP 800-90 Random Bit Generator
Hardware key management for every cryptographic core in your system. Keys are generated, derived and wrapped inside the core, and software manages them by slot number without ever reading them.
Keys enter on dedicated import ports and leave on dedicated key ports, so software names keys by slot number and never reads one
Keys are held in labeled key slots that no bus can read. Each label records the type, length, use and origin of the key.
A CTR_DRBG with AES-256 (NIST SP 800-90A) is seeded from an on-chip entropy source with SP 800-90B health tests. It reseeds from fresh entropy before every request.
SP 800-108 counter and feedback modes with CMAC or HMAC, HKDF, and the SP 800-56C one-step and two-step functions.
AES key wrap with padding (SP 800-38F) protects each key together with its label. Keys stored outside the core return with their purpose and permissions intact.
Keys leave only on dedicated key ports. Each port can be limited to the key types that its consumer core uses.
The core refuses any operation that the label of a key does not allow.
Each alarm input can erase all keys and lock the core, or report only. The response is set at build time.
Known-answer self-tests at reset, a life cycle with a test state that operational keys can never enter, and zeroization of every key.
Every algorithm in every configuration passes NIST's ACVTS test vectors. An ACVP harness with validation support is available as an option.
The countermeasure configuration masks every key from end to end and runs AES on the masked StealthAES engine. StealthAES's countermeasures are tested beyond 1 billion traces with TVLA. This configuration offers the AES-based algorithms, which are CMAC, key wrap, the CMAC-based key derivations and the random bit generator.
| Random Bits | CTR_DRBG with AES-256 (SP 800-90A), with an on-chip entropy source and SP 800-90B health tests |
| Key Derivation | SP 800-108 counter and feedback modes, HKDF, and SP 800-56C one-step and two-step derivation |
| Key Wrap | KW and KWP (SP 800-38F) |
| MAC and Hash | CMAC, HMAC-SHA-2, and SHA-256, SHA-384 and SHA-512 |
| Key Storage | 32 labeled key slots of up to 64 bytes, configurable from 4 to 256 |
| Interfaces | AXI4-Lite host interface, with key, import, seed and alarm ports |
| Software | StealthAPI library and Linux driver |
| Deliverables | Verilog or VHDL RTL, a test suite with NIST ACVP vectors, a C header and documentation |
| AMD Versal AI Edge | Microchip PolarFire SoC | Altera Agilex 5 | |
|---|---|---|---|
| All Algorithms | |||
| Maximum Frequency | 210 MHz | 120 MHz | 145 MHz |
| Logic | 22,122 LUT6 | 43,784 4LUT | 15,985 ALM |
| Flip-Flops | 18,216 | 19,692 | 25,217 |
| Block RAM | 21 RAMB36 | 40 LSRAM | 40 M20K |
| Without SHA-2 and HMAC | |||
| Maximum Frequency | 210 MHz | 120 MHz | 140 MHz |
| Logic | 16,695 LUT6 | 31,797 4LUT | 10,969 ALM |
| Flip-Flops | 12,991 | 14,528 | 18,646 |
| Block RAM | 21 RAMB36 | 40 LSRAM | 40 M20K |
| Countermeasure Configuration | |||
| Maximum Frequency | 195 MHz | 105 MHz | 145 MHz |
| Logic | 28,860 LUT6 | 57,441 4LUT | 19,550 ALM |
| Flip-Flops | 26,506 | 28,372 | 29,571 |
| Block RAM | 30 RAMB36 | 58 LSRAM | 54 M20K |
Post-place-and-route results for the core alone on a mid-range device of each family. Results vary with device, tools and design. At 210 MHz, the core completes up to 196,000 key wraps, 203,000 key unwraps and 258,000 256-bit key derivations per second. Rates scale with the clock frequency of each family. StealthKey is available for AMD Versal, UltraScale+, UltraScale and 7 Series, Microchip PolarFire, PolarFire SoC, SmartFusion 2 and IGLOO2, and Altera Agilex, Arria 10, Stratix 10 and Cyclone 10 FPGAs, and for ASICs.
A test suite including the NIST ACVP test vectors of every algorithm.
Direct key delivery to StealthAES, StealthSHA, StealthPQ and StealthMem, in Verilog or VHDL, with comprehensive documentation.
Decades of cryptographic experience, with dedicated integration support.
Designed for commercial, aerospace and defense applications.
Contact StealthCores for area and performance figures for your target device, and for help choosing the configuration that fits your design.