SHA-2 and SHA-3 Hash, HMAC and KMAC Engine
Every SHA-2 and SHA-3 hash function, SHAKE and cSHAKE, and HMAC and KMAC in hardware, in one compact core at one round per clock, with the same interfaces and DMA framework as StealthAES.
SHA-2 and SHA-3 engines behind one AXI4-Stream interface, with each HMAC and KMAC key's state computed when the key is loaded
SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224 and SHA-512/256 (FIPS 180-4), selected per operation.
SHA3-224, SHA3-256, SHA3-384 and SHA3-512 with SHAKE128 and SHAKE256 (FIPS 202), and cSHAKE128 and cSHAKE256 (SP 800-185).
HMAC (FIPS 198-1) and KMAC128 and KMAC256 (SP 800-185), for both generating and verifying a MAC. Each key's state is computed once, when the key is loaded.
The SHA-2 and SHA-3 engines each complete one round every clock cycle, for full throughput on every stream.
Compares a digest or MAC with the expected value in hardware, in constant time.
AXI4-Stream data with direct, AXI4-Lite or scatter-gather DMA control, using the same interfaces and DMA framework as StealthAES. Delivered in Verilog and VHDL.
Key states and buffers are cleared on command or at reset.
Build SHA-2, SHA-3 or both, or just the algorithms your design uses, to fit your area budget.
| Hash | SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224 and SHA-512/256 (FIPS 180-4); SHA3-224, SHA3-256, SHA3-384 and SHA3-512 (FIPS 202), selected per operation |
| XOF | SHAKE128 and SHAKE256 (FIPS 202); cSHAKE128 and cSHAKE256 (SP 800-185) |
| MAC | HMAC (FIPS 198-1) and KMAC128 and KMAC256 (SP 800-185), generation and constant-time verification |
| Throughput | One round per clock: up to 3.19 Gbps (SHA-256), 4.68 Gbps (SHA-512), 18.4 Gbps (SHA3-256) and 22.7 Gbps (SHAKE128) per stream |
| Interfaces | AXI4-Stream input and output; direct, AXI4-Lite or scatter-gather DMA control |
| Verification | A test suite including NIST CAVP test vectors |
| Algorithms | AMD Versal AI Edge | Microchip PolarFire SoC | Altera Agilex 5 |
|---|---|---|---|
| SHA-224/256SHA-256 throughput | 3.19 Gbps3,454 LUT6 | 1.73 Gbps5,731 4LUT | 2.09 Gbps2,707 ALM |
| SHA-384/512SHA-512 throughput | 4.68 Gbps5,904 LUT6 | 2.40 Gbps9,529 4LUT | 2.72 Gbps4,278 ALM |
| SHA-2 familySHA-512 throughput | 4.11 Gbps6,410 LUT6 | 2.02 Gbps11,692 4LUT | 2.53 Gbps4,639 ALM |
| SHA-3 familySHA3-256 throughput | 18.4 Gbps7,263 LUT6 | 8.16 Gbps13,432 4LUT | 12.7 Gbps6,606 ALM |
| SHA-2 and SHA-3SHA3-256 throughput | 13.4 Gbps12,743 LUT6 | 6.80 Gbps25,248 4LUT | 9.97 Gbps9,983 ALM |
Post-place-and-route results for the core alone on a mid-range device of each family; results vary with device, tools and design. StealthSHA is available for AMD Versal, UltraScale+, UltraScale and 7 Series, Microchip PolarFire, PolarFire SoC, SmartFusion 2 and IGLOO2, and Altera Agilex, Arria 10, Stratix 10 and Cyclone 10 FPGAs, and for ASICs.
A test suite including NIST CAVP test vectors for every algorithm family.
The interfaces and DMA framework of StealthAES, in Verilog and VHDL, with comprehensive documentation.
Decades of cryptographic experience, with dedicated integration support.
Designed for commercial, industrial and defense applications.
Contact StealthCores for area and performance figures for your target device, and for help choosing the configuration that fits your design.