ECDSA and ECDH Elliptic-Curve Cryptography Engine
Full offload of ECDSA and ECDH on the NIST P-384 and P-256 curves in a compact design. Private keys remain in secure internal key slots behind a simple AXI4-Lite interface.
Whole elliptic-curve operations behind one AXI4-Lite interface, with private keys held in internal key slots
Key generation, signing and verification as specified in FIPS 186-5.
Shared-secret computation as specified in SP 800-56A, with full validation of the public key of the peer.
The curve is selected for each operation. A smaller configuration supports P-384 alone.
A low logic count on every FPGA family, with the arithmetic in the DSP blocks of the device.
Private keys are generated in internal key slots and used from there. The host cannot read them.
An AXI4-Lite host interface with an interrupt controls every operation. Optional key ports connect to StealthKey.
Every multiplication by a secret scalar checks its invariant and its result. An operation that fails a check gives no output.
Keys and working data are cleared on command, and working memory is cleared at the end of every operation.
Every algorithm passes NIST's ACVTS test vectors. An ACVP harness with validation support is available as an option.
An optional configuration adds design measures against power analysis, electromagnetic analysis and fault injection. It blinds every scalar and holds each private key in two shares. A detected fault zeroizes the core and locks it until a hardware reset.
| Signatures | ECDSA key generation, signing and verification (FIPS 186-5) |
| Key Agreement | ECDH shared-secret computation with public-key validation (SP 800-56A) |
| Curves | NIST P-384 and P-256 (SP 800-186) |
| Public Keys | Full validation, with compressed public keys supported in hardware |
| Key Storage | Up to 16 internal key slots |
| Interfaces | AXI4-Lite host interface, with optional key ports for StealthKey |
| Software | StealthAPI library, Linux driver, OpenSSL provider and wolfSSL integration |
| Complete Standalone Core | AMD Versal AI Edge | Microchip PolarFire SoC | Altera Agilex 5 |
|---|---|---|---|
| Maximum Frequency | 435 MHz | 190 MHz | 220 MHz |
| Logic | 1,430 LUT6 | 3,959 4LUT | 1,321 ALM |
| Flip-Flops | 1,802 | 2,798 | 1,979 |
| Block RAM | 2.5 RAMB36 | 8 LSRAM, 6 uSRAM | 5 M20K |
| DSP Blocks | 28 | 38 | 26 |
| P-384 Sign | 545 | 189 | 284 |
| P-384 Verify | 531 | 185 | 277 |
| P-384 Shared Secret | 622 | 218 | 324 |
| P-256 Sign | 884 | 310 | 454 |
| P-256 Verify | 860 | 303 | 441 |
| P-256 Shared Secret | 1,000 | 355 | 513 |
| Countermeasure Configuration | |||
| Maximum Frequency | 405 MHz | 185 MHz | 225 MHz |
| Logic | 1,485 LUT6 | 4,108 4LUT | 1,394 ALM |
| P-384 Sign | 344 | 125 | 197 |
| P-384 Verify | 494 | 180 | 283 |
| P-384 Shared Secret | 377 | 138 | 215 |
Post-place-and-route results for the core alone on a mid-range device of each family. Results vary with device, tools and design. Sign, verify and shared-secret rows give operations per second. StealthEC is available for AMD Versal, UltraScale+, UltraScale and 7 Series, Microchip PolarFire, PolarFire SoC, SmartFusion 2 and IGLOO2, and Altera Agilex, Arria 10, Stratix 10 and Cyclone 10 FPGAs, and for ASICs.
Decades of cryptographic implementation experience with dedicated integration support and comprehensive documentation.
A compact design that delivers fast elliptic-curve operations on every major FPGA family.
A complete standalone core, with optional key ports for StealthKey and a configuration for P-384 alone.
NIST standards verified implementation ensuring reliable and trusted security for commercial and defense applications.
Contact StealthCores for area and performance figures for your target device, and for help choosing the configuration that fits your design.